The present invention relates generally to transistor devices and, more particularly, to low voltage and ultra-low voltage latches.
In modern computer systems, power density and scalability issues represent some of the most significant obstacles to increased system performance. For reliability, the supply voltage Vdd must come down. In addition, to control leakage current, the threshold voltage must come up. Consequently, performance is being rapidly squeezed between the two. In addition, with the emergence of an electronics market that stresses portability, compact size, lightweight and the capability for prolonged remote operation, a demand has arisen for low power and ultra-low power transistor devices and systems.
One of the most important transistor devices in any system is the data latch, also called simply a xe2x80x9clatchxe2x80x9d. However, in the prior art, latches have represented a significant challenge to the designer seeking to reduce power consumption and increase system performance for a given supply voltage. Latches have proven a particularly difficult problem in the low voltage and ultra-low power regimes.
One reason prior art latches have been such a problem is that standard CMOS technology was used to make the transistors in prior art latches. This resulted in transistors with threshold voltages of 500millivolts. The fact that prior art latches included transistors with threshold voltages this high meant that the ability of prior art latches to operate at lower supply voltages was significantly limited. Indeed, prior art latches typically had to operate at relatively high minimum supply voltages of 800millivolts or more in order to achieve reasonable performance. Consequently, the voltage scalability of prior art latches, i.e., the ability of prior art latches to operate over a wide range of supply voltages, was very limited. As a result, the performance of prior art latches was far from ideal.
What is needed is a latch that can operate at very low supply voltages and therefore has increased voltage scalability and the potential for better performance and lower power consumption.
According to one embodiment of the invention, latch components are comprised of low threshold transistors. In addition, according to one embodiment of the invention, to overcome leakage current and ensure proper latch operation, the channel widths of the low threshold transistors making up the feedback components of the latch are larger than the channel widths of the low threshold transistors making up the storage components of the latch. This embodiment of the invention allows for minimum supply voltages of 120 millivolts; an improvement of over six hundred percent compared with the typical prior art minimum voltage requirement of 800 millivolts.
In another embodiment of the present invention, a method and structure for providing low voltage latches includes using low threshold transistors having consistent channel dimensions and the use of multi-inverter feedback structures. In this embodiment of the invention, all the transistors included in a latch have the same channel dimensions, i.e., the same channel length and width. In order to meet this requirement and still provide a feedback signal of sufficient strength to overcome leakage effects and insure proper latch operation, latches according to this embodiment of the invention include feedback stages with multiple inverters. By using transistors of the same channel length and width in the latches of the invention, the voltage scalability of the latch is increased significantly over that of prior art latches. This embodiment of the invention allows for minimum supply voltages of 85 millivolts; an improvement of over nine hundred percent compared with the typical prior art minimum voltage requirement of 800 millivolts.
In addition to ensuring all of the transistors making up a latch have the same channel dimensions, according to the invention, the minimum voltage requirement of the latch is further reduced by designing the latch with uniform stack height components, i.e., components with equal numbers of transistors in series. This technique is in sharp contrast to the prior art teachings. A particularly significant increase in latch performance is obtained when the latch is designed to include both uniform stack height and transistors of uniform channel dimensions in accordance with the invention. This embodiment of the invention allows for minimum supply voltages of 60 millivolts; an improvement of over thirteen hundred percent compared with the typical prior art minimum voltage requirement of 800 millivolts.
As a result of these and other features discussed in more detail below, latches designed according to the principles of the present invention require significantly lower supply voltages and have significantly improved voltage scalability and performance compared to prior art latches. Consequently, latches designed according to the principles of the invention can better meet the needs of modern electronics markets than prior art methods or structures.
It is to be understood that both the foregoing general description and following detailed description are intended only to exemplify and explain the invention as claimed.